SC28L92_7 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 07 — 19 December 2007 48 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
7.3.13 Interrupt Vector Register (IVR; 68xxx mode) or General Purpose register
(GP; 80xxx mode)
This register stores the Interrupt Vector. It is initialized to 0x0F on hardware reset and is
usually changed from this value during initialization of the SC28L92. The contents of this
register will be placed on the data bus when IACKN is asserted LOW or a read of address
0xC is performed.
When not operating in the 68xxx mode, this register may be used as a general purpose
one byte storage register. A convenient use could be to store a shadow of the contents of
another SC28L92 register (IMR, for example).
7.3.14 Counter/timer registers
The CTPU and CTPL hold the eight MSBs and eight LSBs, respectively, of the value to be
used by the counter/timer in either the counter or timer modes of operation. The minimum
value which may be loaded into the CTPU/CTPL registers is 0x0002. Note that these
registers are write only and cannot be read by the CPU.
In the timer mode, the C/T generates a square wave whose period is twice the value (in
C/T clock periods) of the CTPU and CTPL. The waveform so generated is often used for a
data clock. The formula for calculating the divisor n to load to the CTPU and CTPL for a
particular 1× data clock is shown in Equation 2.
(2)
Often this division will result in a non-integer number; 26.3, for example. One can only
program integer numbers in a digital divider. Therefore, 26 would be chosen. This gives a
baud rate error of 0.3/26.3 which is 1.14 %; well within the ability asynchronous mode of
operation.
The C/T will not be running until it receives an initial start counter command (read at
address A3 to A0 = 1110). After this, while in timer mode, the C/T will run continuously.
Receipt of a start counter command (read with A3 to A0 = 1110) causes the counter to
terminate the current timing cycle and to begin a new cycle using the values in CTPU and
CTPL. If the value in CTPU and CTPL is changed, the current half-period will not be
affected, but subsequent half periods will be affected.
Table 61. IVR/GP - Interrupt vector register or general purpose register (address 0xC)
bit allocation
7 6 5 4 3 2 1 0
interrupt vector (68xxx mode) or one byte storage (80xxx mode)
Table 62. CTPU - Counter/Timer Preset Upper register (address 0x6) bit description
Bit Symbol Description
7:0 - The upper eight (8) bits for the 16-bit counter/timer preset register
Table 63. CTPL - Counter/Timer preset Lower register (address 0x7) bit description
Bit Symbol Description
7:0 - The lower eight (8) bits for the 16-bit counter/timer preset register
n
counter/timer clock frequency
216× desired baud rate()×
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