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SC28L92A1BS,551

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P73
SC28L92_7 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 07 — 19 December 2007 34 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
[1] Duty cycle of 16× clock is 50 % ± 1%.
7.3.2.2 Clock Select Register channel B (CSRB)
Table 36. Bit rate generator characteristics
[1]
Crystal or clock = 3.6864 MHz.
Normal rate (baud) Actual 16× clock (kHz) Error (%)
50 0.8 0
75 1.2 0
110 1.759 −0.069
134.5 2.153 0.059
150 2.4 0
200 3.2 0
300 4.8 0
600 9.6 0
1050 16.756 −0.260
1200 19.2 0
1800 28.8 0
2000 32.056 0.175
2400 38.4 0
4800 76.8 0
7200 115.2 0
9600 153.6 0
19200 307.2 0
38400 614.4 0
Table 37. CSRB - Clock select register channel B (address 0x9) bit description
Bit Symbol Description
7 to 4 - Receiver clock select. The baud rate clock for the channel B receiver is as
shown in
Table 35, except as follows:
1110 = IP6 - 16×
1111 = IP6 - 1×
The receiver clock is always a 16× clock except for CSRB[7:4] = 1111
3 to 0 - Transmitter clock select. The baud rate clock for the channel A transmitter is
as shown in
Table 35, except as follows:
1110 = IP5 - 16×
1111 = IP5 - 1×
The transmitter clock is always a 16× clock except for CSRB[3:0] = 1111
SC28L92_7 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 07 — 19 December 2007 35 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
7.3.3 Command registers
7.3.3.1 Command Register channel A (CRA)
CRA is a register used to supply commands to channel A. Multiple commands can be
specified in a single write to CRA as long as the commands are non-conflicting, e.g., the
enable transmitter and reset transmitter commands cannot be specified in a single
command word.
Table 38. CRA - Command register channel A (address 0x2) and
CRB - Command register channel B (address 0xA) bit allocation
7 6 5 4 3 2 1 0
channel command code disable Tx enable Tx disable Rx enable Rx
Table 39. CRA - Command register channel A (address 0x2) bit description
Bit Symbol Description
7 to 4 - Miscellaneous commands. Execution of the commands in the upper four bits
of this register must be separated by 3 X1 clock edges. Other reads or writes
(including writes to the lower four bits) may be inserted to achieve this
separation. A description of miscellaneous commands is given in
Table 40.
3 - Disable channel A transmitter. This command terminates transmitter operation
and reset the TxDRY and TxEMT status bits. However, if a character is being
transmitted or if a character is in the Tx FIFO when the transmitter is disabled,
the transmission of the character(s) is completed before assuming the inactive
state.
2 - Enable channel A transmitter. Enables operation of the channel A transmitter.
The TxRDY and TxEMT status bits will be asserted if the transmitter is idle.
1 - Disable channel A receiver. This command terminates operation of the
receiver immediately-a character being received will be lost. The command
has no effect on the receiver status bits or any other control registers. If the
special multi-drop mode is programmed, the receiver operates even if it is
disabled. See
Section 6.3.10.
0 - Enable channel A receiver. Enables operation of the channel A receiver. If not
in the special wake-up mode, this also forces the receiver into the search for
start-bit state.
Table 40. Miscellaneous commands
Command Description
0000 No command.
0001 Reset MR pointer. Causes the channel A MR pointer to point to MR1.
0010 Reset receiver. Resets the channel A receiver as if a hardware reset had been
applied. The receiver is disabled and the FIFO is flushed.
0011 Reset transmitter. Resets the channel A transmitter as if a hardware reset had
been applied.
0100 Reset error status. Clears the channel A received break, parity error, and overrun
error bits in the status register (SRA[7:4]). Used in character mode to clear OE
status (although RB, PE and FE bits will also be cleared) and in block mode to clear
all error status after a block of data has been received.
0101 Reset channel A break change interrupt. Causes the channel A break detect
change bit in the interrupt status register (ISR[2]) to be cleared to zero.
SC28L92_7 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 07 — 19 December 2007 36 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
7.3.3.2 Command Register channel B (CRB)
CRB is a register used to supply commands to channel B. Multiple commands can be
specified in a single write to CRB as long as the commands are non-conflicting, e.g., the
enable transmitter and reset transmitter commands cannot be specified in a single
command word.
The bit definitions for this register are identical to the bit definitions for CRA, with the
exception of miscellaneous commands 0xE and 0xF which are used for Power-down
mode. These two commands are not used in CRB. All other control actions that apply to
CRA also apply to CRB.
0110 Start break. Forces the TxDA output LOW (spacing). If the transmitter is empty the
start of the break condition will be delayed up to two bit times. If the transmitter is
active the break begins when transmission of the character is completed. If a
character is in the Tx FIFO, the start of the break will be delayed until that
character, or any other loaded subsequently are transmitted. The transmitter must
be enabled for this command to be accepted.
0111 Stop break. The TxDA line will go HIGH (marking) within two bit times. TxDA will
remain HIGH for one bit time before the next character, if any, is transmitted.
1000 Assert RTSN. Causes the RTSN output to be asserted (LOW).
1001 Negate RTSN. Causes the RTSN output to be negated (HIGH).
1010 Set time-out mode on. The receiver in this channel will restart the C/T as each
receive character is transferred from the shift register to the Rx FIFO. The C/T is
placed in the counter mode, the start counter or stop counter commands are
disabled, the counter is stopped, and the counter ready bit, ISR[3], is reset. (see
also watchdog timer description in the receiver
Section 6.3.7.)
1011 Set MR pointer to 0x0.
1100 Disable time-out mode. This command returns control of the C/T to the regular start
counter or stop counter commands. It does not stop the counter, or clear any
pending interrupts. After disabling the time-out mode, a stop counter command
should be issued to force a reset of the ISR[3] bit.
1101 Not used.
1110 Power-down mode on. In this mode, the DUART oscillator is stopped and all
functions requiring this clock are suspended. The execution of commands other
than disable Power-down mode (1111) requires a X1/CLK. While in the
Power-down mode, do not issue any commands to the CR except the disable
Power-down mode command. The contents of all registers will be saved while in
this mode. It is recommended that the transmitter and receiver be disabled prior to
placing the DUART into Power-down mode. This command is in CRA only.
1111 Disable Power-down mode. This command restarts the oscillator. After invoking this
command, wait for the oscillator to start up before writing further commands to the
CR. This command is in CRA only. For maximum power reduction input pins should
be at V
SS
or V
DD
.
Table 40. Miscellaneous commands
…continued
Command Description
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P73

SC28L92A1BS,551

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Buy SC28L92A1BS,551
Manufacturer:
NXP Semiconductors
Description:
IC UART DUAL W/FIFO 48HVQFN
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New from this manufacturer.
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