Tsi721 Datasheet 10 April 4, 2016
Integrated Device Technology
• 32 outstanding S-RIO NREAD/maintenance read requests to S-RIO network
• 32 outstanding S-RIO NWRITE_R/maintenance write/doorbell requests to S-RIO network
• 12-KB completion reassembly buffer
• 8 windows from PCIe to S-RIO with 8 zones (sub windows) per window
• 8 windows from S-RIO to PCIe
• Initiates and receives the following S-RIO transactions:
— NREAD
— SWRITE/NWRITE/NWRITE_R
— Maintenance read and write
—Port-write
— Doorbell
— Type 8 response
— Type 13 response
• Initiates and receives the following PCIe transactions:
—MWr
—MRd
—Cpl
—CplD
• Round-robin scheduling between Mapping Engine, Block DMA Engine, and Messaging traffic to the S-RIO link
• Round-robin scheduling between Mapping Engine, Block DMA Engine, and Messaging traffic to the PCIe link
• Forward bridge
— Connects PCIe root complex to S-RIO network
— PCIe Type 0 configuration header
1.2.4 Messaging Features
• 8 Tx queues with one dedicated messaging DMA engine per Tx queue
• 8 Rx queues with one dedicated messaging DMA engine per Rx queue
• Descriptor prefetch per Tx queue
• 32 outstanding PCIe requests to root complex
• 8-KB message segment reassembly buffer per Tx queue
• Round-robin scheduling among Tx queues
• One outstanding message per Tx queue
• 16 receive contexts per Rx queue
1.2.5 Block DMA Engine Features
• 8 DMA channels
• Each DMA channel can perform DMA writes from root complex to S-RIO network, or DMA reads from S-RIO network to
root complex
— DMA from PCIe port to PCIe port is not supported
— DMA from S-RIO port to S-RIO port is not supported
