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TSI721A1-16GILV

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66
Tsi721 Datasheet 22 April 4, 2016
Integrated Device Technology
2.9 GPIO Signals
Table 7: GPIO Signals
Name Pin Type Description
GPIO[15:0] IO Asynchronous general purpose I/O.
• Each GPIO pin can be configured as a general purpose I/O pin.
• Each pin can be configured as either an input or an output
• When configured as an output, GPIO[0] is asserted high when
BDMA/SMSG/PC2SR/SR2PC has an uncorrectable ECC error or S-RIO MAC
has a non-data memory uncorrectable ECC error
• When configured as an output, GPIO[1] is asserted high when Tsi721 PCIe
port is not in the data link active state
• When configured as an output, GPIO[2] is asserted high when Tsi721 has an
active interrupt (for more information, see Figure 18 and Figure 19)
• When configured as an output, GPIO[15:3] can be programmed through
software
GPIO[12:0] are used as power-up pins as displayed in Ta ble 8. These signals
must remain stable for 4000 REFCLKP/REFCLKN cycles after RSTn is
de-asserted. They are ignored after reset.
Table 8: GPIO Mapping to Power-up Signals
GPIO Pin Name
(Primary Function)
Power-up Pin Name
a
(Secondary Function)
a. For more information about these signals, see Power-up Signals.
GPIO[3:0] I2C_SA[3:0]
GPIO[4] I2C_DISABLE
GPIO[5] I2C_SEL
GPIO[6] I2C_MA
GPIO[7] SP_SWAP_RX
GPIO[8] SP_SWAP_TX
GPIO[9] SP_HOST
GPIO[10] SP_DEVID
GPIO[12:11] CLKSEL[1:0]
Tsi721 Datasheet 23 April 4, 2016
Integrated Device Technology
2.10 Power-up Signals
Table 9: Power-Up Signals
Name Pin Type Description
CLKMOD I-PU Clock mode. When high, Tsi721 uses “PCIe common clocked mode.” When low,
it uses “PCIe non-common clocked mode.” It is a static signal.
CLKSEL[1:0] IO REFCLKP/REFCLKN clock frequency select; PCCLKP/PCCLKN clock
frequency select when in PCIe non-common clock mode.
• 0b11 = 125 MHz
• 0b10 = 100 MHz
• 0b01 = 156.25 MHz
•Others = Reserved
When a 100-MHz clock is used, S-RIO SerDes rates of 1.25/2.5/5 Gbaud are
supported.
When a 125/156.25-MHz clock is used, S-RIO SerDes rates of
1.25/2.5/3.125/5 Gbaud are supported.
When either a 100/125/156.25-MHz clock is used, PCIe SerDes rates of
2.5/5 Gbaud are supported.
These power-up signals are multiplexed with GPIO[12:11]. It is a static signal.
I2C_DISABLE IO Disable I
2
C register loading after reset. When asserted, Tsi721 does not attempt
to load register values from an EEPROM over the I
2
C bus.
0 = Enable boot load from EEPROM
1 = Disable boot load from EEPROM
This power-up signal is multiplexed with GPIO[4]. It is a static signal.
I2C_MA IO I
2
C multi-byte address mode. If I2C_DISABLE == 0 (that is, download registers
from EEPROM) then:
0 = Tsi721 uses 1-byte addressing for EEPROM
1 = Tsi721 uses 2-byte addressing for EEPROM
Else I2C_DISABLE == 1 (do not download from EEPROM)
• 0 = Tsi721 is boot loaded by the PCIe root complex after reset
• 1 = Tsi721 is boot loaded by an external I2C master after reset
This power-up signal is multiplexed with GPIO[6]. It is a static signal.
I2C_SA[3:0] IO I2C slave address. The values on these pins represent the values for the 7-bit
address of the Tsi721 when acting as an I
2
C slave.
These signals, in combination with the I2C_SEL signal, determine the address of
the EEPROM to boot from (see I2C_SEL pin description).
The values on these pins can be overridden after a reset by writing to the I2C
Slave Configuration Register.
These power-up signals are multiplexed with GPIO[3:0]. It is a static signal.
Tsi721 Datasheet 24 April 4, 2016
Integrated Device Technology
I2C_SEL IO I
2
C pin select. Combined with the I2C_SA[1,0] pins, Tsi721 will determine the
lower 2 bits of the 7-bit address of the EEPROM address it boots from.
When asserted, the I2C_SA[1:0] pins represent the two LSBs of the 7-bit
EEPROM slave address when Tsi721 acts as a I
2
C master downloading from an
EEPROM. The EEPROM slave address is as follows:
A6 = 1
A5 = 0
A4 = 1
A3 = 0
A2 = 0
A1 = I2C_SA[1]
A0 = I2C_SA[0]
When de-asserted, the I2C_SA[1:0] pins are ignored and the lower two bits of
the EEPROM address default to 00. The values of the EEPROM address can be
overridden by software after initialization.
This power-up signal is multiplexed with GPIO[5]. It is a static signal.
SP_DEVID IO S-RIO base deviceID control
When the SP_HOST pin is high, it configures the reset value of the RapidIO
Base deviceID CSR: the LSB of the CSR’s BASE_ID and LAR_BASE_ID fields
are set to SP_DEVID, while other bits of these fields are set to 0.
When the SP_HOST pin is low and SP_DEVID is high, it configures the reset
value of the RapidIO Base deviceID CSR: the CSR’s BASE_ID and
LAR_BASE_ID fields are set to all ones.
When the SP_HOST pin is low and SP_DEVID is low, it configures the reset
value of the RapidIO Base deviceID CSR: the CSR’s BASE_ID field is set to
0xFE and the CSR’s LAR_BASE_ID field are set to 0x00FE.
This signal is multiplexed with GPIO[10]. It is a static signal.
SP_HOST IO S-RIO host / slave control. This signal sets the reset value of the HOST bit of the
RapidIO Port General Control CSR.
0 = Tsi721 is an S-RIO slave.
1 = Tsi721 is an S-RIO host.
This signal is multiplexed with GPIO[9]. It is a static signal.
SP_SWAP_RX IO S-RIO receive lane swap. This signal sets the reset value of the SWAP_RX[1:0]
bits of RapidIO PLM Port Implementation Specific Control Register.
0 = Disable S-RIO port receive lane swap; that is, set the SWAP_RX[1:0]
register bits to 0b00.
1 = Enable S-RIO port receive 4x lane swap; that is, set the SWAP_RX[1:0]
register bits to 0b10.
This signal is multiplexed with GPIO[7].
Table 9: Power-Up Signals (Continued)
Name Pin Type Description
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66

TSI721A1-16GILV

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Buy TSI721A1-16GILV
Manufacturer:
IDT
Description:
PCI Interface IC PCIe-to-Rapid IO Bridge
Lifecycle:
New from this manufacturer.
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