Tsi721 Datasheet 46 April 4, 2016
Integrated Device Technology
1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The
sinusoidal jitter can have any amplitude and frequency in the unshaded region of the following figure. The sinusoidal jitter
component is included to ensure margin for the low frequency jitter, wander, noise, crosstalk and other variable system
effects.
Figure 8: S-RIO Single Frequency Sinusoidal Jitter Limits
Table 24: Level I Receiver Input Jitter Tolerance Specifications
Characteristic Symbol Reference Minimum Typical Maximum Units
Bit error ratio BER - - - 10
-12
-
Bounded high probability jitter R_BHPJ Section
9.4.3.8
- - 0.37 UIpp
Sinusoidal jitter, maximum R_SJ-max Section
9.4.3.8
--8.5UIpp
Sinusoidal jitter, high frequency R_SJ-hf Section
9.4.3.8
--0.1UIpp
Total Jitter (Does not include sinusoidal
jitter)
R_TJ Section
9.4.3.8
- - 0.55 UIpp
Total jitter tolerance
1
R_JT - - - 0.65 UIpp
Eye mask R_X1 Section
9.4.3.8
--0.275UI
Eye mask R_Y1 Section
9.4.3.8
--100mV
Eye mask R_Y2 Section
9.4.3.8
--800mV
Tsi721 Datasheet 47 April 4, 2016
Integrated Device Technology
3.7.4.0.2 Level I Receiver Eye Diagram
For each baud rate at which the a LP-Serial receiver is specified to operate, the receiver meets the corresponding Bit Error
Ratio specification in Ta ble 25 when the eye pattern of the receiver test signal (exclusive of sinusoidal jitter) falls entirely within
the unshaded portion of the Receiver Input Compliance Mask displayed in Figure 9. The eye pattern of the receiver test signal
is measured at the input pins of the receiving device with the device replaced with a 100 Ohm + 5% differential resistive load.
Figure 9: S-RIO Level I Receiver Input Mask
3.7.4.1 5 Gbps LP-Serial Links
This chapter describes the requirements for Level II RapidIO LP-Serial short and medium electrical interfaces of nominal baud
rates of 5.0. Gbps using NRZ coding (thus, 1 bit per symbol at the electrical level). A compliant device must meet all of the
requirements listed below. The electrical interface is based on a high speed low voltage logic with a nominal differential
impedance of 100 Ohm. Connections are point-to-point balanced differential pair and signaling is unidirectional.
Table 25: Level I Far-End (Rx) Template Intervals
Characteristic Symbol
Far-End
Value
Units
Eye mask R_X1 0.275 UI
Eye mask R_Y1 100 mV
Eye mask R_Y2 800 mV
High probability jitter R_HPJ 0.37 UIpp
Total Jitter (Does not include sinusoidal
jitter)
R_TJ 0.55 UIpp
Tsi721 Datasheet 48 April 4, 2016
Integrated Device Technology
3.7.4.2 Explanatory Note on Level II Transmitter and Receiver Specifications
AC electrical specifications are provided for transmitters and receivers. The parameters for the AC electrical specifications are
guided by the OIF CEI Electrical and Jitter Inter-operability agreement for CEI-6G-SR and CEI-6G-LR.
OIF CEI-6G-SR and CEI-6G-LR have similar application goals to S-RIO, as described in Section 10.1, “Level II Application
Goals.” The goal of this standard is that electrical designs for S-RIO can reuse electrical designs for OIF CEI-6G, suitably
modified for applications at the baud intervals and runs described herein.
3.7.4.3 Level II Electrical Specifications
The electrical interface is based on high speed, low voltage logic with nominal differential impedance of 100 Ohm. Connections
are point-to-point balanced differential pair and signaling is unidirectional.
3.7.4.3.1 Level II Transmitter Characteristics
Level II LP-Serial transmitter electrical and timing specifications are stated in the text and tables of this section.
The differential return loss must be better than A0 from f0 to f1 and better than
A0 + Slope*log10(f/f1)
Where f is the frequency from f1 to f2 (see section 8.5.11, Figure 8-12 of the RapidIO Specification (Rev. 2.1). Differential
return loss is measured at compliance points T and R. If AC coupling is used, then all components (internal or external) are to
be included in this requirement. The reference impedance for the differential return loss measurements is 100 Ohm.
Common mode return loss measurement must be better than -6dB between a minimum frequency of 100 MHz and a
maximum frequency of 0.75 times the baud rate. The reference impedance for the common mode return loss is 25 Ohm.
The Tsi721 satisfies the specification requirement that the 20%-80% rise/fall time of the transmitter, as measured at the
transmitter output, in each case has a minimum value 30 ps.
Similarly, the timing skew at the output of an LP-Serial transmitter between the two signals that comprise a differential pair
does not exceed 10 ps at 5.0.

TSI721A1-16GILV

Mfr. #:
Manufacturer:
IDT
Description:
PCI Interface IC PCIe-to-Rapid IO Bridge
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New from this manufacturer.
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