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TSI721A1-16GILV

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66
Tsi721 Datasheet 4 April 4, 2016
Integrated Device Technology
List of Figures
Figure 1: Block Diagram............................................................................................................................................................................................. 12
Figure 2: Defense/Aerospace Application ................................................................................................................................................................14
Figure 3: Video and Imaging Application .................................................................................................................................................................15
Figure 4: Wireless Application ..................................................................................................................................................................................16
Figure 5: Ballmap.......................................................................................................................................................................................................18
Figure 6: S-RIO Definition of Transmitter Amplitude and Swing................................................................................................................................39
Figure 7: S-RIO Transition Symbol Transmit Eye Mask.............................................................................................................................................44
Figure 8: S-RIO Single Frequency Sinusoidal Jitter Limits........................................................................................................................................46
Figure 9: S-RIO Level I Receiver Input Mask............................................................................................................................................................. 47
Figure 10: Transition and Steady State Symbol Eye Mask.......................................................................................................................................... 51
Figure 11: Level II Receiver Input Compliance Mask................................................................................................................................................... 56
Figure 12: HCSL to REFCLKP/N / PCCLKP/N............................................................................................................................................................58
Figure 13: LVDS to REFCLKP/N / PCCLKP/N............................................................................................................................................................. 58
Figure 14: LVPECL to REFCLKP/N / PCCLKP/N........................................................................................................................................................58
Figure 15: LVPECL to REFCLKP/N / PCCLKP/N........................................................................................................................................................59
Figure 16: I2C Interface Signal Timings.......................................................................................................................................................................60
Figure 17: Package Diagrams...................................................................................................................................................................................... 63
Tsi721 Datasheet 5 April 4, 2016
Integrated Device Technology
List of Tables
Table 1: Signal Types ............................................................................................................................................................................................... 17
Table 2: PCIe Signals............................................................................................................................................................................................... 19
Table 3: S-RIO Signals............................................................................................................................................................................................. 20
Table 4: General Signals .......................................................................................................................................................................................... 20
Table 5: I2C Signals.................................................................................................................................................................................................. 21
Table 6: JTAG Interface Signals...............................................................................................................................................................................21
Table 7: GPIO Signals..............................................................................................................................................................................................22
Table 8: GPIO Mapping to Power-up Signals........................................................................................................................................................... 22
Table 9: Power-Up Signals.......................................................................................................................................................................................23
Table 10: Power Supply Signals.................................................................................................................................................................................26
Table 11: Absolute Maximum Ratings........................................................................................................................................................................27
Table 12: Recommended Operating Conditions.........................................................................................................................................................28
Table 13: Power Consumption.................................................................................................................................................................................... 28
Table 14: Power Supply Sequencing Ramp Times ....................................................................................................................................................29
Table 15: 3.3V LVTTL DC Operating Characteristics at Recommended Operating Condition of 3.3V ...................................................................... 30
Table 16: 2.5V LVTTL DC Operating Characteristics at Recommended Operating Condition of 2.5V ...................................................................... 30
Table 17: Decoupling Recommendation.....................................................................................................................................................................31
Table 18: PCIe Differential Receiver Specifications ................................................................................................................................................... 31
Table 19: PCIe Differential Transmitter Specifications................................................................................................................................................34
Table 20: Level I Short Run Transmitter AC Timing Specifications............................................................................................................................42
Table 21: Level I Long Run Transmitter AC Timing Specifications............................................................................................................................. 43
Table 22: Level I Near-End (Tx) Template Intervals ................................................................................................................................................... 44
Table 23: Level I Receiver Electrical Input Specifications .......................................................................................................................................... 45
Table 24: Level I Receiver Input Jitter Tolerance Specifications.................................................................................................................................46
Table 25: Level I Far-End (Rx) Template Intervals ..................................................................................................................................................... 47
Table 26: Level II Short Run Transmitter Output Electrical Specifications.................................................................................................................. 49
Table 27: Level II Medium Run Transmitter Output Electrical Specifications ............................................................................................................. 50
Table 28: Level II Medium Run Near-End (Tx) Template Intervals............................................................................................................................. 52
Table 29: Level II Short Run Receiver Electrical Input Specifications........................................................................................................................53
Table 30: Level II MR Receiver Electrical Input Specifications...................................................................................................................................55
Table 31: Level II Far-End (Rx) Template Intervals .................................................................................................................................................... 56
Table 32: PCCLKP/N and REFCLKP/NClock Electrical Characteristics .................................................................................................................... 57
Table 33: JTAG and Test Interface AC Specifications................................................................................................................................................ 59
Table 34: I2C Interface AC Specifications..................................................................................................................................................................60
Table 35: GPIO Interface AC Specifications...............................................................................................................................................................61
Table 36: RSTn Signal AC Specifications................................................................................................................................................................... 61
Table 37: Package Dimensions.................................................................................................................................................................................. 62
Table 38: Junction to Ambient Characteristics – Theta JB/JC....................................................................................................................................64
Table 39: Junction to Ambient Characteristics – Theta JA.........................................................................................................................................64
Tsi721 Datasheet 6 April 4, 2016
Integrated Device Technology
About this Document
Topics discussed include the following:
• Overview
• Document Conventions
• Revision History
Overview
The Tsi721 Datasheet provides signal, electrical, and packaging information about the Tsi721. It is intended for hardware
engineers who are designing system interconnect applications with the device.
Document Conventions
This document uses the following conventions.
Non-differential Signal Notation
Non-differential signals are either active-low or active-high. An active-low signal has an active state of logic 0 (or the lower
voltage level), and is denoted by a lowercase “n”. An active-high signal has an active state of logic 1 (or the higher voltage
level), and is not denoted by a special character. The following table illustrates the non-differential signal naming convention.
Differential Signal Notation
Differential signals consist of pairs of complement positive and negative signals that are measured at the same time to
determine a signal’s active or inactive state (they are denoted by “_p” and “_n”, respectively). The following table illustrates the
differential signal naming convention.
State Single-line signal Multi-line signal
Active low NAMEn NAMEn[3]
Active high NAME NAME[3]
State Single-line signal Multi-line signal
Inactive NAME_p = 0
NAME_n = 1
NAME_p[3] = 0
NAME_n[3] = 1
Active NAME_p = 1
NAME_n = 0
NAME_p[3] is 1
NAME_n[3] is 0
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66

TSI721A1-16GILV

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Description:
PCI Interface IC PCIe-to-Rapid IO Bridge
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