Tsi721 Datasheet 38 April 4, 2016
Integrated Device Technology
8. A single combination of PLL BW and peaking is specified for 2.5 Gbps implementations. For 5.0 Gbps, two combinations of
PLL BW and peaking are specified to permit designers to make a trade-off between the two parameters. If the PLL’s minimum
BW is >= 8MHz, the up to 3.0 dB of peaking is permitted. If the PLL’s minimum BW is related to >= 5.0 MHz, then a tighter
peaking value of 1.0 dB must be met. In both cases, the maximum PLL BW is 16 MHz.
9. Low swing output, defined by VTX-DIFF-PP-LOW must be implemented as displayed in Figure 4-27 of the PCI Express Base
Specification (Rev. 2.1) with no de-emphasis.
10.For 5.0 Gbps, de-emphasis timing jitter must be removed. An additional HPF function must be applied as displayed in
Figure 4-21 of PCI Express Base Specification (Rev. 2.1). This parameter is measured by accumulating a record of 106 UI
while the DUT outputs a compliance pattern. TMIN-PULSE is defined to be nominally 1 UI wide and is bordered on both
sides by pulses of the opposite polarity. Refer to Figure 4-29 of PCI Express Base Specification (Rev. 2.1).
11.Root complex Tx de-emphasis is configured from Upstream controller. Downstream Tx de-emphasis is set through a
command, issues at 2.5 Gbps. For information, refer to the appropriate location in Section 4.2 of PCI Express Base
Specification (Rev. 2.1).
3.7.3 RapidIO SerDes Characteristics
3.7.3.1 Overview
The Tsi721’s SerDes are in full compliance to the RapidIO AC specifications for the LP-Serial physical layer [5]. This section
provides those specifications for reference only; the user should see the specification for complete requirements.
Chapter 9 of the specification, “1.25 Gbaud, 2.5 Gbaud, and 3.125 Gbaud LP-Serial Links” defines Level I links compatible
with the 1.3 version of the Physical Layer Specification, that supports throughput rates of 1.25, 2.5, and 3.125 Gbps.
Chapter 10 of the specification, “5 Gbaud and 6.25 Gbaud LP-Serial Links” defines Level II links that support throughput rates
of 5 and 6.25 Gbps.
A Level I link should:
• Allow 1.25, 2.5, or 3.125 Gbps rates
• Support AC coupling
• Support hot plug
• Support short run (SR) and long run (LR) links achieved with two transmitters
• Support single receiver specification that will accept signals from both the short run and long run transmitter specifications
• Achieve Bit Error Ratio of lower than 10
-12
per lane
A Level II link should:
• Allow 5 Gbps baud rates
• Support AC coupling and optional DC coupling
• Support hot plug
• Support short run (SR), and medium run (MR) links achieved with two transmitters and two receivers
• Achieve Bit Error Ratio of lower than 10
-15
per lane but test requirements will be verified to 10
-12
per lane
Together, these specifications allow for solutions ranging from simple chip-to-chip interconnect to board-to-board interconnect
driving two connectors across a backplane. The faster and wider electrical interfaces specified here are required to provide
higher density and/or lower cost interfaces.
The short run defines a transmitter and a receiver that should be used mainly for chip-to-chip connections on either the same
printed circuit board or across a single connector. This covers the case where connections are made to a mezzanine
(daughter) card. The smaller swings of the short run specification reduces the overall power used by the transceivers.
