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TSI721A1-16GILV

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66
Tsi721 Datasheet 25 April 4, 2016
Integrated Device Technology
SP_SWAP_TX IO S-RIO transmit lane swap. This signal sets the reset value of the SWAP_TX bit
of RapidIO PLM Port Implementation Specific Control Register.
0 = Disable S-RIO port transmit lane swap.
1 = Enable S-RIO port transmit lane swap.
This signal is multiplexed with GPIO[8]. It is a static signal.
SR_BOOT I-PD Boot from S-RIO. It can be asserted high only when I2C_DISABLE is also high.
1 = The Tsi721 S-RIO link can start training immediately after a fundamental
reset and Tsi721 automatically sets the SRBOOT_CMPL bit of Device Control
Register.
0 = The Tsi721 S-RIO link can start training only after software sets the
SRBOOT_CMPL bit.
It is a static signal.
STRAP_RATE[2:0] I-PU S-RIO link rate. These signals control the reset value of the BAUD_SEL field of
the RapidIO Port Control 2 CSR . Note that the BAUD_SEL encoding is different
than that of STRAP_RATE.
• 0b111 = 5 Gbaud
• 0b110 = 2.5 Gbaud
• 0b101 = 1.25 Gbaud
• 0b010 = 3.125 Gbaud
• Others: Reserved
It is a static signal.
Table 9: Power-Up Signals (Continued)
Name Pin Type Description
Tsi721 Datasheet 26 April 4, 2016
Integrated Device Technology
2.11 Power Supply Signals
Table 10: Power Supply Signals
Name Pin Type Description
VDD PWR 1.0V core power
VDDIO PWR 3.3/2.5V power for LVTTL IO
AVDD10 PWR 1.0V PCIe and S-RIO SerDes analog power supply
AVDD25 PWR 2.5V PCIe and S-RIO SerDes analog power supply
AVTT PWR 1.5V PCIe and S-RIO SerDes transmitter analog voltage
VSS GND Shared digital and analog ground
PCBIAS IO Reference for the corresponding PCIe SerDes bias currents and PLL calibration
circuitry. A 200 Ohm 1% 100ppm/C precision resistor should be connected from
this pin to ground and isolated from any source of noise injection.
SRBIAS IO Reference for the corresponding S-RIO SerDes bias currents and PLL
calibration circuitry. A 200 Ohm 1% 100ppm/C precision resistor should be
connected from this pin to ground and isolated from any source of noise
injection.
Tsi721 Datasheet 27 April 4, 2016
Integrated Device Technology
3. Electrical Characteristics
Topics discussed include the following:
• Absolute Maximum Ratings
• Recommended Operating Conditions
• Power Consumption
• Power Supply Sequencing
• DC Operating Characteristics
• Decoupling Recommendation
• AC Timing Specifications
3.1 Absolute Maximum Ratings
Table 11: Absolute Maximum Ratings
a
a. Stresses outside the absolute ratings can cause permanent damage to the device and affect its functional performance. Exposure to absolute
rating conditions for extended periods can affect reliability.
Symbol Parameter Minimum Maximum Units
VDDIO 3.3/2.5V I/O voltage with respect to VSS -0.5 3.6 V
VDD 1.0V core voltage with respect to VSS -0.5 1.10 V
AVDD10 1.0V analog voltage with respect to AVSS -0.5 1.10 V
AVDD25 2.5V analog voltage with respect to AVSS -0.5 2.75 V
AVTT 1.5V analog voltage for SerDes transmitter with
respect to AVSS
-0.5 2.75 V
T
BIAS
Temperature under bias -40 125 C
T
STG
Storage temperature -65 150 C
T
JN
Junction temperature - 125 C
I
OUT
(for VDDIO =
3.3/2.5V)
DC output current - 30 mA
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66

TSI721A1-16GILV

Mfr. #:
Buy TSI721A1-16GILV
Manufacturer:
IDT
Description:
PCI Interface IC PCIe-to-Rapid IO Bridge
Lifecycle:
New from this manufacturer.
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