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TSI721A1-16GILV

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66
Tsi721 Datasheet 34 April 4, 2016
Integrated Device Technology
7. ZRX-HIGH-IMP-DC-NEG and ZRX-HIGH-IMP-DC-POS are defined respectively for negative and positive voltages at the
input of the Receiver. Transmitter designers need to comprehend the large difference between >0 and <0 Rx impedances
when designing Receiver detect circuits.
8. The LRX-SKEW parameter exists to handle repeaters that regenerate Refclk and introduce differing numbers of skips on
different lanes.
3.7.2 PCIe Differential Transmitter Specifications
Table 19 lists the electrical characteristics for the PCIe differential transmitters in the Tsi721. Parameters are defined
separately for 2.5 Gbps and 5.0 Gbps implementations. Table 19 is duplicated from the PCI Express Base Specification
(Rev. 2.1) Section 4.3.3.5 Table 4-9 on page 252.
Table 19: PCIe Differential Transmitter Specifications
Symbol Parameter
2.5 Gbps 5.0 Gbps
Unit NotesMin. Max. Min. Max.
UI Unit interval 399.88 400.12 199.94 200.06 ps The specified UI is equivalent to a
tolerance of +/- 300ppm for each Refclk
source. Period does not account for
SSC induced variations. See Note 1.
V
TX-DIFF-PP
Differential p-p Tx voltage
swing
0.8 1.2 0.8 1.2 V As measured with compliance test load.
Defined as 2*|V
TXD+
- V
TXD-
|
V
TX-DIFF-PP-LOW
Low power differential p-p
Tx voltage swing
0.4 1.2 0.4 1.2 V As measured with compliance test load.
Defined as 2*|V
TXD+
- V
TXD-
|. See Note
9.
V
TX-DE-RATIO-3.
5DB
Tx de-emphasis level
ratio
3.0 4.0 3.0 4.0 dB See Section 4.3.3.9 of PCI Express
Base Specification (Rev. 2.1) and Note
11 for information.
V
TX-DE-RATIO-6DB
Tx de-emphasis level
ratio
N/A N/A 5.5 6.5 dB See Section 4.3.3.9 of PCI Express
Base Specification (Rev. 2.1) and Note
11 for information.
T
MIN-PULSE
Instantaneous lone pulse
width
Not specified 0.9 - UI Measured relative to rising/falling
pulses. See Notes 2,10 and Figure 4-29
of PCI Express Base Specification
(Rev. 2.1)
T
TX-EYE
Transmitter eye including
all jitter sources
0.75 - 0.75 - UI Does not include SSC or Refclk jitter.
Includes Rj at 10-12. See Notes 2, 3, 4
and 10. Note that 2.5 Gbps and 5.0
Gbps use different jitter determination
methods.
T
TX-EYE-MEDIAN
-to-MAX-JITTER
Maximum time between
the jitter median and
maximum deviation from
the median
- 0.125 Not specified UI Measured differentially at zero crossing
points after applying the 2.5 Gbps clock
recovery function. See Note 2.
Tsi721 Datasheet 35 April 4, 2016
Integrated Device Technology
T
TX-HF-DJ-DD
Tx deterministic jitter >
1.5 MHz
Not specified - 0.15 UI Deterministic jitter only. See Notes 2 and
10.
T
TX-LF-RMS
TX RMS jitter < 1.5 MHz Not specified 3.0 - ps
RMS
Total energy measured over a 10 kHz -
1.5 MHz range
T
TX-RISE-FALL
Transmitter rise and fall
time
0.125 - 0.15 - UI Measured differentially from 20% to
80% of swing. See Note 2 and Figure
4-28 of PCI Express Base Specification
(Rev. 2.1)
T
RF-MISMATCH
Tx rise/fall mismatch Not specified - 0.1 UI Measured from 20% to 80%
differentially. See Note 2.
BW
TX-PLL
Maximum Tx PLL
bandwidth
- 22 - 16 MHz Second order PLL jitter transfer
bounding function. See Note 6.
BW
TX-PLL-LO-3DB
Minimum Tx PLL BW for
3dB peaking
1.5 - 8 - MHz Second order PLL jitter transfer
bounding function. See Notes 6 and 8.
BW
TX-PLL-LO-1DB
Minimum Tx PLL BW for
1dB peaking
Not specified 5 - MHz Second order PLL jitter transfer
bounding function. See Notes 6 and 8.
PKG
TX-PLL1
Tx PLL peaking with
8MHz BW
Not specified - 3.0 dB See Note 8.
PKG
TX-PLL2
Tx PLL peaking with
5MHz BW
Not specified - 1.0 dB See Note 8.
RL
TX-DIFF
Tx package plus Si
differential return loss
10 -
10 for
0.05-1.25
GHz
8 for
1.25-2.5
GHz
- dB For more information, refer to Figure
4-34 of PCI Express Base Specification
(Rev. 2.1)
RL
TX-CM
Tx package plus Si
common mode return loss
6 - 6 - dB Measured over 0.05 - 1.25 GHz range
for 2.5 Gbps and 0.05 - 2.5 GHz range
for 5.0 Gbps (S
11
parameter)
Z
TX-DIFF-DC
DC differential Tx
impedance
80 120 - 120 W Low impedance defined during
signaling. Parameter is captured for 5.0
GHz by RL
TX-DIFF
.
V
TX-CM-AC-PP
Tx AC common mode
voltage (5.0 Gbps)
Not specified - 100 mV See Note 5.
V
TX-CM-AC-P
TX AC common mode
voltage (2.5 Gbps)
20 - Not specified mV See Note 5.
Table 19: PCIe Differential Transmitter Specifications (Continued)
Symbol Parameter
2.5 Gbps 5.0 Gbps
Unit NotesMin. Max. Min. Max.
Tsi721 Datasheet 36 April 4, 2016
Integrated Device Technology
I
TX-SHORT
Transmitter short-circuit
current limit
- 90 - 90 mA The total current transmitter can supply
when shorted to ground.
V
TX-DC-CM
Transmitter DC
common-mode voltage
0 3.6 0 3.6 V The allowed DC common-mode voltage
at the Transmitter pins under any
condition.
V
TX-CM-DC-ATIV
E-IDLE-DELTA
Absolute delta of DC
common-mode voltage
during L0 and Electrical
Idle
0 100 0 100 mV |V
TX-CM-DC[during L0]
-
V
TX-CM-Idle-DC[during Electrical Idle]
| <=
100mV
V
TX-CM-DC
= DC
(avg)
of |V
TX-D+
+
V
TX-D-
|/2
V
TX-CM-Idle-DC
= DC
(avg)
of |V
TX-D+
+
V
TX-D-
|/2 [Electrical Idle]
V
TX-CM-DC-LINE-
DELTA
Absolute delta of DC
common-mode voltage
between D+ and D-
025025mV|V
TX-CM-DC-D+[during L0]
- V
TX-CM-DC-D-
[during L0]
| <= 25mV
V
TX-CM-DC-D+
= DC
(avg)
of |V
TX-D+
|
[during L0]
V
TX-CM-DC-D-
= DC
(avg)
of |V
TX-D-
|
[during L0]
V
TX-IDLE-DIFF_A
C-p
Electrical idle differential
peak output voltage
020020mVV
TX-IDLE-DIFFp
= |V
TX-Idle-D+
- V
TX-Idle-D-
|
<= 20mV. Voltage must be high pass
filtered to remove any DC component.
V
TX-IDLE-DIFF_DC
DC electrical idle
differential output voltage
Not specified 0 5 mV V
TX-IDLE-DIFF-DC
= |V
TX-Idle-D+
-
V
TX-Idle-D-
| <= 5 mV. Voltage must be
low pass filtered to remove any AC
component. Filter characteristics
complementary to those for
V
TX-IDLE-DIFF-AC-p
V
TX-RCV-DETECT
The amount of voltage
change allowed during
receiver detection
- 600 - 600 mV The total amount of voltage change in a
positive direction that a Transmitter can
apply to sense whether a low
impedance Receiver is present. Note:
Receivers display substantially different
impedance for V
IN
< 0 versus V
IN
> 0.
See Table 4-12 of PCI Express Base
Specification (Rev. 2.1) for more
information.
T
TX-IDLE-MIN
Minimum time spent in
electrical idle
20 - 20 - ns Minimum time a Transmitter must be in
Electrical Idle
Table 19: PCIe Differential Transmitter Specifications (Continued)
Symbol Parameter
2.5 Gbps 5.0 Gbps
Unit NotesMin. Max. Min. Max.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66

TSI721A1-16GILV

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Manufacturer:
IDT
Description:
PCI Interface IC PCIe-to-Rapid IO Bridge
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