TSI721A1-16GILV Datasheet TSI721A1-16GILV, TSI721A1-16GCLV, TSI721A1-16GILY | P7-P9

Tsi721 Datasheet 7 April 4, 2016

Integrated Device Technology

Object Size Notation

•A byte is an 8-bit object.

•A PCIe word is a 16-bit object.

•A PCIe doubleword (DW) is a 32-bit object.

•An S-RIO word is a 32-bit object.

•An S-RIO doubleword (Dword) is a 64-bit object.

Numeric Notation

• Hexadecimal numbers are denoted by the prefix 0x (for example, 0x04).

• Binary numbers are denoted by the prefix 0b (for example, 0b010).

• Registers that have multiple iterations are denoted by {x..y} in their names; where x is first register and address, and y is the

last register and address. For example, REG{0..1} indicates there are two versions of the register at different addresses:

REG0 and REG1.

Symbols

Revision History

April 4, 2016

• Added GCLV, GILH, and GILV part numbers to Ordering Information

May 5, 2014

• Updated the description of the V

IN_DIFF

parameter in Table 32

December 3, 2012

• Updated Ordering Information with production ordering numbers

February 28, 2012

• Added a footnote to Absolute Maximum Ratings, and removed the minimum rating for T

from the same section

• Added T

and a footnote to Recommended Operating Conditions

December 16, 2011

• Updated the minimum and maximum values for AVDD10 in Recommended Operating Conditions

• Added Power Consumption data

• Changed the Moisture Sensitivity Level to 4

This symbol indicates important configuration information or suggestions.

This symbol indicates procedures or operating levels that may result in misuse or damage to the

device.

Tsi721 Datasheet 8 April 4, 2016

Integrated Device Technology

1. Device Overview

Topics discussed include the following:

• Overview

• Features

• Block Diagram

• Typical Applications

1.1 Overview

IDT is the leading supplier of RapidIO

and PCI Express Interconnect solutions, providing a broad portfolio of switches,

bridges, IP, and development platforms for defense aerospace, video, imaging, and wireless markets. The Tsi721 is IDT's

solution for hardware-based PCIe Gen2 to RapidIO Gen2 protocol conversion in a bridging device.

The Tsi721 converts transactions from PCIe to RapidIO, and vice versa, and provides full line rate bridging at 20 Gbaud. Using

the Tsi721, designers can develop heterogeneous systems that leverage the peer-to-peer networking performance of RapidIO

while using multiprocessor clusters that may be only PCIe enabled. In addition, applications that require large amounts of data

transferred efficiently without processor involvement can be executed using the full line rate of the Tsi721’s Block DMA Engine

and Messaging Engine.

Key to the Tsi721 is the hardware bridging functionality that converts PCIe transactions to RapidIO, and vice versa. The Tsi721

supports PCIe non-transparent bridging for transaction mapping. The device has both RapidIO and PCIe endpoints embedded

in the bridge, and each of its Block DMA/Messaging DMA channels can buffer up to 8 KB of data on the PCIe side.

1.2 Features

The Tsi721 supports the following features.

1.2.1 PCIe Features

• PCIe 2.1 standard compliant

• 5/2.5 Gbaud link speed

• x4/x2/x1 link width

• 128- and 256-byte maximum payload

• Advanced error reporting

• Internal error reporting

• Lane reversal

• Automatic polarity inversion

• Dynamic port width: x4 drops to x1

• ECRC support

• INTx, MSI, and MSI-X support

Tsi721 Datasheet 9 April 4, 2016

Integrated Device Technology

• Single virtual channel, VC0

• Single traffic class, TC0

— Generates only PCIe posted/non-posted TLPs with TC0

— Generates only PCIe Cpl/CplD TLPs with TC matching their requests

— Accepts PCIe TLPs with any TC

•Four BARs

— Prefetchable BAR with 32- or 64-bit addressing for PCIe-to-S-RIO bridging

— Non-prefetchable BAR with 32- or 64-bit addressing for PCIe-to-S-RIO bridging

— Non-prefetchable BAR with 32-bit addressing for PCIe MWr to S-RIO doorbell bridging

— Non-prefetchable BAR with 32-bit addressing for Tsi721 internal register access

• Initial credit advertisement programmable through EEPROM

• Dynamic control of credits through registers

• Starvation prevention based on flow control credit updates

• Large buffers

— 12 KB/2 KB/12 KB input buffers for up to 127 posted/non-posted/completion TLPs

— 12 KB/2 KB/12 KB output buffers for up to 128 posted/non-posted/completion TLPs

• Debug features

— Slave analog loopback through a control register

— Slave loopback using TS1/TS2 ordered sets

— Master loopback

— Internal error reporting

— ECC protection on internal memories

1.2.2 S-RIO Features

• S-RIO 2.1 standard compliant

• 5/3.125/2.5/1.25 Gbaud link speed

• x4/x2/x1 link width

• 34-, 50-, and 66-bit addressing

• 16 destID filters

• 8 S-RIO flows

• 9-KB ingress buffer (32 x 288)

• 9-KB egress buffer (32 x 288)

• Lane reversal

• Lane polarity inversion

1.2.3 Bridging Features

• Store and forward from PCIe to S-RIO

• Store and forward from S-RIO to PCIe

• Line rate support for 64 byte and larger packets

• 32 outstanding PCIe requests to root complex

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P57 P58-P60 P61-P63 P64-P66

TSI721A1-16GILV

Mfr. #:

Buy TSI721A1-16GILV

Manufacturer:

IDT

Description:

PCI Interface IC PCIe-to-Rapid IO Bridge

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

TSI721A1-16GILV

TSI721A1-16GILV

Products related to this Datasheet