Linear Technology's LTC6950 is a low-phase noise integer-N frequency synthesizer core with clock distribution. The LTC6950 delivers the low-phase noise clock signals demanded in high-frequency, high-resolution data acquisition systems.

The frequency synthesizer contains a full-low-noise PLL core with a programmable reference divider (R), a programmable feedback divider (N), a phase/frequency detector (PFD), and a low-noise charge pump (CP). The clock distribution section of the LTC6950 delivers up to five outputs based on the VCO input. Each output is individually programmed to divide the VCO input frequency by any integer from 1 to 63 and to delay the output by 0 to 63 VCO clock cycles. Four of the outputs feature very-low-noise, low-skew LVPECL logic signals capable of operation up to 1.4 GHz. The fifth output is selectable as either an LVDS (800 MHz) or CMOS (250 MHz) logic type. This output is also programmed to produce an output signal based on either the VCO input or the reference divider output.

EZSync Synchronization on LTC6950’s Clock Dividers

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LTC6950 Code