Texas Instruments' LMK03328 is an ultra-low-noise clock generator with two fractional-N frequency synthesizers with integrated VCOs, flexible clock distribution/fanout, and pin-selectable configuration states stored in on-chip EEPROM. The device can generate multiple clocks for various multi-gigabit serial interfaces and digital devices, reduces BOM costs and board area, and improves reliability by replacing multiple oscillators and clock distribution devices. The ultra-low-jitter reduces bit error rate (BER) in high-speed serial links.

For each PLL, a differential/single-ended clock or crystal input can be selected as the PLL reference clock. The selected PLL reference input can be used to lock the VCO frequency at an integer or fractional multiple of the reference input frequency. The VCO frequency for the respective PLLs can be tuned between 4.8 GHz and 5.4 GHz. Both PLL/VCOs are equivalent in performance and functionality. Each PLL offers the flexibility to select a predefined or user-defined loop bandwidth, depending on the needs of the application. Each PLL has a post-divider that can be selected between divide-by 2, 3, 4, 5, 6, 7, or 8.