Vishay Siliconix's SiRA20DP N-channel 25 V MOSFET has the lowest R_DS(ON) in its class. It reduces switching-related power loss by optimizing total gate charge (Q_g), gate-drain charge (Q_gd), and Q_gd/gate-source charge (Q_gs) ratio. The very low Q_gd "miller" charge enables passing through plateau voltage faster.  It is packaged in a conventional PowerPAK^® SO-8 design.  Presenting higher power density without changing the package dimension and pin configuration. The 10-mil clip reduces package contributed resistance by 66% and maximizes the performance of the silicon.