IDT's 8SLVD1204I and IDT8SLVD1204-33I are high-performance differential LVDS fanout buffers. The devices are designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVD1204I is characterized to operate from a 2.5 V power supply and the IDT8SLVD1204-33I from a 3.3 V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the devices ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and four low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The devices are optimized for low power consumption and low additive phase noise.
8SLVD1204-33I Features
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8SLVD1204I Features |
- Four low skew, low additive jitter LVDS output pairs
- Two selectable differential clock input pairs
- Differential PCLKx, nPCLKx pairs can accept the following differential input levels: LVDS, LVPECL
- Maximum input clock frequency: 2 GHz
- LVCMOS/LVTTL interface levels for the control input select pin
- Output skew: 20 ps (max)
- Propagation delay: 310 ps (max)
- Low additive phase jitter, RMS; fREF = 156.25 MHz, VPP = 1 V, 10 kHz to 20 MHz: 100 fs (max)
- Full 3.3 V supply voltage
- Lead-free (RoHS 6), 16-lead VFQFN packaging
- -40°C to +85°C ambient operating temperature
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- Four low skew, low additive jitter LVDS output pairs
- Two selectable differential clock input pairs
- Differential PCLK, nPCLK pairs can accept the following differential input levels: LVDS, LVPECL
- Maximum input clock frequency: 2 GHz
- LVCMOS/LVTTL interface levels for the control input select pin
- Output skew: 20 ps (max)
- Propagation delay: 300 ps (max)
- Low additive phase jitter, RMS; fREF = 156.25 MHz, VPP = 1 V, 10 kHz to 20 MHz: 95 fs (max)
- Full 2.5 V supply voltage
- Lead-free (RoHS 6), 16-lead VFQFN packaging
- -40°C to +85°C ambient operating temperature
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