Integrated Device Technology features their highly programmable clock generator and jitter attenuator IC featuring less than 200 fs of phase noise, providing valuable system design margin for 10 Gbps interfaces in wireline and wireless communication networks. The additional phase noise margin eases system design constraints, allowing engineers to minimize bit error rates (BER) while lowering overall system costs.

The 8T49N240 features the ability to produce virtually any common output frequency from virtually any input frequency. The highly flexible, high-performance clock generator and jitter attenuator is ideal for 10 Gbps or multi-lane 40 Gbps and 100 Gbps timing applications where 300 fs of phase noise is typically the maximum acceptable amount allowed at the physical ports. The 200 fs phase noise specification of the 8T49N240 provides ample noise margin, enabling engineers to simplify their clock tree designs and utilize lower cost PCBs.

The 8T49N240 is complemented by IDT's proven Timing Commander™ software – a free, intuitive program that allows users to configure the device with ease by simply clicking on blocks, entering desired values, and sending the configuration to the device. IDT also offers a web-based tool that allows customers to generate custom part numbers in seconds to match their specific configurations.

The 8T49N240 features a 6 mm x 6 mm package footprint, requiring considerably less PCB area than most other solutions with this level of performance and flexibility. The device is also suitable for 25 Gbps and 28 Gbps interfaces.