74LVC8T595 Dual Supply Shift Register

By Nexperia 122

74LVC8T595 Dual Supply Shift Register

Nexperia's 74LVC8T595 dual supply shift register is an 8-bit serial-in or parallel-out configuration with a storage register and 3-state outputs. Separate clocks exist for the shift and storage register. The data in the shift register is transferred to the storage register on a positive-going transition of the STCP input. If both clocks are connected, the shift register is always one clock pulse ahead of the storage register.

VCC(A) and VCC(B) can be supplied at any voltage between 1.1 V and 5.5 V making the device suitable for translating between any of the voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins MR, SHCP, STCP, OE, DS and Q7S are referenced to VCC(A) and pins Qn are referenced to VCC(B).

The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging current through the device when it is powered down. In suspend mode when VCC(A) is at GND level, the Qn outputs are in the high-impedance OFF-state.

Features
  • Wide supply voltage range:
    • VCC(A): 1.1 V to 5.5 V
    • VCC(B): 1.1 V to 5.5 V
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-12A (1.1 V to 1.3 V)
    • JESD8-11A (1.4 V to 1.6 V)
    • JESD8-7 (1.65 V to 1.95 V)
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8C (3.0 V to 3.6 V)
    • JESD12-6 (4.5 V to 5.5 V)
  • Suspend mode
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • ±24 mA output drive (VCC(A) = VCC(B) = 3.0 V)
  • Inputs accept voltages up to 5.5 V
  • IOFF circuitry provides partial power-down mode operation
  • Multiple package options
  • Specified from -40°C to +85°C and -40°C to +125°C
  • ESD protection:
    • HBM ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 4000 V
    • CDM JESD22-C101E exceeds 1000 V
Applications
  • I²C
  • Cellular phones
  • LCD televisions
  • STB
  • Personal computing
  • Batterymanagement

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