Silicon Labs’ Si539x any-frequency jitter attenuators feature a fully integrated reference, enhancing system reliability, and performance while simplifying PCB layout in high-speed networking designs.
The Si539x jitter attenuators are purpose-built to address the demanding reference clock requirements of 100/200/400/600/800G designs, providing more than 40 percent margin to the stringent jitter requirements of 56G PAM-4 SerDes used in state-of-the-art Ethernet switch SoCs, PHYs, FPGAs, and ASICs while providing a solution that is future-proofed for emerging 112G SerDes designs.
Features
- Space savings
- Users designing high-port-count optical and Ethernet line cards place a premium on reducing overall board space. By using a jitter attenuator with an integrated reference, developers can minimize the PCB footprint by more than 35 percent. As an added benefit, an integrated reference eliminates the need for the keep-out area under the crystal, enabling denser clock routing
- Frequency flexibility and clock distribution
- The Si539x devices generate any combination of frequencies from 100 Hz to 1028 MHz on up to 12 differential clock outputs, eliminating the need for standalone clock generators and clock buffers. These benefits enable clock-tree-on-a-chip clocking while eliminating the additive jitter associated with discrete clock tree solutions
- Improved system reliability and performance
- The Si539x jitter attenuators integrate a highly reliable crystal that has been fully tested over temperature and pre-screened for activity dips. The Si539x devices have been fully qualified over a broad range of reliability tests including shock, vibration, temperature cycling, and crystal aging
- High acoustic emission noise immunity
- The Si539x device’s integrated crystal package construction isolates and protects the crystal from acoustic emissions (AE) noise, ensuring reliable operation and consistent frequency response over time
Applications
- Fronthaul/backhaul
- Metro/core
- Data center applications
