Silicon Labs offers a broad portfolio of frequency flexible ultra-low jitter timing products that enable hardware designers to simplify clock generation, distribution, and jitter attenuation with Xilinx FPGAs and SoCs with ample design margins, meeting stringent timing requirements for high-speed serial communications applications.

Silicon Labs clocks/jitter attenuators/network synchronizers use proprietary DSPLL and MultiSynth technologies to generate any combination of frequencies with ultra-low jitter, enabling some of the best clock tree integration in their class. Clock buffers provide low-jitter, low-skew clock distribution with integrated format/voltage level translation. PCIe® clocks/buffers combine Gen 1/2/3/4/5 compliance with on-chip series termination, simplifying design. XO/VCXOs are factory-customizable to any frequency with samples available in one to two weeks.

Silicon Labs timing solutions are widely used in several Xilinx evaluation boards and development kits, listed below: